Sources
This book draws heavily on the following source:
"Reiner Pope — Chip design from the bottom up" — Dwarkesh Podcast, May 22, 2026
- YouTube: https://youtu.be/oIk3R-sMX5o
- Transcript: https://www.dwarkesh.com/p/reiner-pope-2
- The Waiting Game — How Inference Economics Shapes the Future of AI. A journey through the memory wall, KV caches, batch economics, speculative decoding, and custom silicon.
- Beyond the Waiting Game — How AI is Learning to Work Around the Memory Wall. The sequel exploring what comes after inference economics — architectures and techniques that reshape how models think.
- The Model That Does Everything — What NVIDIA's Diffusion LM Means for Inference. A critical analysis of NVIDIA's Nemotron-Labs-Diffusion.
- Dadda, L. (1965). "Some schemes for parallel multipliers." Alta Frequenza, 34:349–356. — The standard Dadda multiplier architecture referenced in Chapter 1.
- Jouppi, N. P., et al. (2017). "In-Datacenter Performance Analysis of a Tensor Processing Unit." ISCA 2017. — The original TPU paper describing systolic array architecture.
- NVIDIA (2024). "NVIDIA B200 GPU Architecture Whitepaper." — FP4 performance claims discussed in Chapter 1.
Reiner Pope is the CEO of MatX, a new AI chip startup. He was previously at Google, where he worked on software efficiency, compilers, and TPU architecture.